The present invention relates to a semiconductor memory device, and more particularly to a clock generating circuit and a method of generating an internal clock having the same or substantially frequency of the external clock, and a data output circuit using the clock generating circuit and method.
In general, a Double Data Rate (DDR) DRAM increases the operation speed of the memory device by outputting two internal clock signals to a data pin for each external clock period at the rising edge of each external clock period. One internal clock signal generated is in phase with the external clock and the other internal clock generated is 180-degree out of phase with the external clock.
However, when the external clock period is shorter, stable performance of the DRAM requires the external clock period to be divided in order to generate an internal clock. The internal operation of the DRAM should then be synchronized with the internal clock, and an output signal to the outside of the DRAM should be synchronized with the external clock. Accordingly, the clock being synchronized with the external clock should be generated based upon the internal clock.
When a new clock is generated and subsequently synchronized with the external clock based upon the internal clock, adjusting the duty between the clocks (which having the same period) becomes difficult due to transistor characteristics.
Accordingly, there is a need for providing a circuit and a method of generating a clock having a same clock period with an exact duty based upon the internal clock.